1. Technical Field
Embodiments of the present invention generally relate to a semiconductor memory device and a method for driving the same, and more particularly to a chip die capable of being stacked, a semiconductor memory device including the chip die, and a method for driving the semiconductor memory device.
2. Related Art
Semiconductor memory devices have been widely used in various electronic appliances. The semiconductor memory device aims to improve its operation speed as well as to implement its miniaturization. Dynamic Random Access Memory (DRAM) serving as a representative semiconductor memory device has been manufactured to improve the operation speed, and is appropriate for a high-speed operation.
Joint Electron Device Engineering Council (JEDEC) serving as a semiconductor standardization organization has selected a wide Input/Output (I/O) scheme considering a parallel-interface Low Power Double Data Rate (LPDDR) and a chip die stack as the next-generation DRAM scheme. A plurality of semiconductor companies persistently makes efforts to develop DRAMs having more improved functions on the basis of JEDEC standard.
With the rapid development of mobile devices, the next-generation DRAMs need to be optimized for such mobile devices. The next-generation DRAMs have been rapidly developed to have smaller sizes and lower power consumption. Specifically, various attempts (e.g., voltage scaling, structural improvement, new I/O signaling, and signal-integration improvement) have been made to achieve low power consumption as well as to compensate for power trade-off suitable for the demand of a high-speed memory.